1. Field of the Invention
The present invention relates generally to programmable logic devices, logic sequencers and microprogram controllers/sequencers and more particularly to an improved family of fully integrated CMOS VLSI micro-sequencer devices which provide an efficient means for implementing state machines and microcoded controller devices.
2. Discussion of the Prior Art
Currently available microprogram sequencer parts offer relatively high speed control blocks for microprogrammed machines. Many of these parts are not programmable, so only a fixed architecture is available to the user. Non-programmable parts can only provide a microcode address output, which then drives the address port of an additional EPROM chip. The result is a lower speed of operation, and a minimum of two chips for operation: a microprogram address sequence generator and a code ROM.
Other available micro-sequencers are once programmable (through fuses), resulting in a higher potential operating speed since all delay paths are contained in one chip. Such fuse based devices are not reprogrammable and generally consume such large amounts of current that the total number of programmable elements per chip is limited by thermal considerations.
Another observation about existing micro-sequencers is that the conditional branching capability is (apparently for reasons of speed) rudimentary. Branching between two different "next address" possibilities is supported, but the decision is based on the logic value of only one input signal, or at most a single programmable AND or OR term. This limited branching capability often causes considerable inconvenience to the use of these parts.
Microprogram sequencers such as the AM2909, AM2911 and AM2910 all from Advanced Micro Devices (AMD) are used to control the sequential execution of microcoded operations in so called "bit slice" computers. These devices provide a microcode address each clock, which address is used to access an external program memory. The outputs of the external program memory control the various components of the bit slice processor. Microprogram address branching in these parts is rudimentary, consisting of a test of the OR of two input pins. In any given clock cycle there are only two possible choices for the next address, the default if the OR is true and a single alternative if the OR is false. A later part from AMD, the AM29PL141 slightly extends this by making the branching decision based on as many as seven input signals, but the decision is still limited to one default address and a single alternative address. A common limitation among the AM2909, AM2911 and AM2910 is the need for an external microcode memory. This limitation is relieved in the AM29PL141 where a small program memory is included on the same chip as the address sequencer.
The logic sequencer is a more general purpose component which is not specialized to the task of microprogram control.
In FIG. 1 a logic sequencer block diagram is shown. This block diagram reflects the current state of the art in logic sequencers. In this diagram there is a clocked pipeline register 100 which receives inputs from the AND/OR logic array 102 and delivers synchronized output data to lines 104 to drive the output pins 108, tristate enable lines 106 for same, and a number of internal feedback lines 110 into the AND/OR array 102. Also driving inputs to the AND/OR array are signals from the external pins 112. The pipeline register 100 is clocked by a signal named CLOCK 114 which comes from an external pin. Such a figure appears in the U.S. Pat. No. 3,566,153 to R. F. Spencer of Texas Instruments (1971). The use of tri-state output control of output drivers is well known in the art.
A circuit typically used to implement the AND/OR logic array 102 of FIG. 1 is shown in an EPROM implementation in FIG. 2. This figure is similar to one found in the U.S. Pat. No. 4,617,479 to R. F. Hartmann et al of Altera (1986). In FIG. 2 the EPROM transistors 220 are programmed by a-means not shown, so that some of the transistors will never conduct whether the gate voltage is zero or +V. Although the cells including the transistors 220 are reprogrammable using techniques well known in the art, they are not reprogrammable during logic function operation of the device. Unprogrammed transistors will conduct when their gates are driven to +V, but not when driven to zero volts. The major elements of FIG. 2 are the input signal circuits 200 which drive the first level of programmable NOR circuits 202 (which perform a programmable negative logic AND function) which in turn drive the second level of NOR gates 204 (which perform a programmable positive logic OR function) which then drive the output signal lines 206. This functional block is universal in the sense that any logic function may be expressed in a "sum of products" form, which means the OR function of some number of AND functions of the input signals. In practice the number of AND functions which may drive the OR function will be limited in any particular implementation. Because of this, some logical functions of the input signals may not be implementable in a given device. A particular type of device, in which the AND functions are programmable, but the subsequent OR functions are not programmable is disclosed in the U.S. Pat. No. 4,124,899 to J. M. Birkner et al of Monolithic Memories Inc. (MMI) (1978).
Although programmable logic devices (PLDs) including PLA's, FPLA's and PAL's are well known in the art and are available in a variety of configurations, such devices suffer from the disadvantages that, as generally depicted in FIG. 1 of the drawings, all of the signals leading into the logic array 102 will have the same structural path through the logic block to the outputs. Therefore, the critical delay from any input to the outputs is about the same. Those skilled in the art will recognize, however, that some of the signals driving into the programmable logic block come from sources inside the chip (thus they will arrive relatively early) while others come from sources off the chip, and will therefore arrive later. For a synchronous logic sequencer this arrangement (of equal delays for early and late inputs) is suboptimal. Internal signals are "early" since they achieve their values shortly after each clock rising edge (clock-to-output-time "tco" of the internal flip-flops), while the external signals are "late" since they accumulate the tco of an external flip-flop plus the extra delay of the input pad electronics plus the delays of any additional gating which might be used. Clearly, some means of using the extra time during which the internal signals are available prior to the arrival of the external signals would enhance the overall speed of a machine.